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AS1116
6 4 L E D D r i v e r w i t h D e ta i l e d E r r o r D e t e c t i o n
D a ta s h e e t
1 General Description
The AS1116 is a compact LED driver for 64 single LEDs or 8 digits of 7-segments. The devices can be programmed via an SPI compatible 3-wire interface. Every segment can be individually addressed and updated separately. Only one external resistor (RSET) is required to set the current. LED brightness can be controlled by analog or digital means. The devices include an integrated BCD code-B/HEX decoder, multiplex scan circuitry, segment and display drivers, and a 64-bit memory. Internal memory stores the shift register settings, eliminating the need for continuous device reprogramming. Additionally the AS1116 offers a diagnostic mode for easy and fast production testing and allows the use of the AS1116 for critical applications. The diagnostic allows to detect individual open or shorted LEDs. The AS1116 features a low shutdown current of typically 200nA, and an operational current of typically 350A. The number of digits can be programmed, the devices can be reset by software, and an external clock is also supported. The device is available in a QSOP-24 and TQFN(4x4)24 package.
2 Key Features
! ! ! ! ! ! ! ! ! ! ! !
10MHz SPI-Compatible Interface Open and Shorted LED Error Detection - Global or Individual Error Detection Hexadecimal- or BCD-Code for 7-Segment Displays 200nA Low-Power Shutdown Current (typ; data retained) Individual Digit Brightness Control Digital and Analog Brightness Control Display Blanked on Power-Up Drive Common-Cathode LED Displays Supply Voltage Range: 2.7 to 5.5V Software Reset Optional External Clock Package: - QSOP-24 and TQFN(4x4)-24
3 Applications
The AS1116 is ideal for seven-segment or dot matrix displays in public information displays at subway, train or bus stations, at airports and also at displays in public , transportation like buses or trains mobile phones, personal electronic and toys.
Figure 1. Typical Application Diagram
8 VDD 2.7V to 5.5V 9.53k ISET SDI DIG0 to DIG7 SEGA-DP 8 GND 8 8 8
AS1116
SDO SDI
AS1116
LD
SDO
I/O
SDI
AS1116
LD
SDO
SCL P I/O I/O I/O
LD
SCL
SCL
Diagnostic readback: open & shorted LEDs
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AS1116
Datasheet - P i n o u t
4 Pinout
Pin Assignments
Figure 2. Pin Assignments (Top View)
SEGD SCL SEGDP
18 SEG E 17 SEGC 16 VDD 15 SEGG 14 SEGB 13 SEGF 7 8 9 10 11 12
DIG1
DIG0
22 SEGDP
21 SEG E
18 SEGG
23 SEGD
20 SEGC
17 SEGB
15 SEGA
16 SEGF
24 SDO
14 SCL
19 VDD
13 ISET
24 23 22 21 20 19
DIG2 1 DIG3 2 GND 3 DIG4 4 DIG5 5 N/C 6
AS1116
DIG7 10 DIG0 2 DIG1 3 DIG2 4 DIG3 5 GND 6 DIG4 7 DIG5 8 DIG6 9 N/C 12 SDI 1 LD 11
AS1116
SDO ISET
SDI
Pin Descriptions
Table 1. Pin Descriptions Pin Name SDI DIG0:DIG7 GND LD N/C ISET QSOP-24 1 2-5, 7-10 6 11 12 13 TQFN(4x4)-24 22 1, 2, 4, 5, 7, 8, 23, 24 3 9 6 10 Description Serial-Data Input. Data is loaded into the internal 16-bit shift register on the rising edge of pin SCL. Digit Drive Lines. Eight digit drive lines that sink current from the display cathode. Ground. Load. Serial Data is loaded into the shift register while this pin is low. The last 16 bits of serial data are latched on the rising edge of this pin. Not Connected. Set Segment Current. Connect to VDD or a reference voltage through RSET to set the peak segment current (see Selecting RSET Resistor Value and Using External Drivers on page 15). Serial-Clock Input. 10MHz maximum rate. Data is shifted into the internal shift register on the rising edge of this pin. Data is clocked out of pin SDO on the rising edge of this pin. Seven Segment and Decimal Point Drive Lines. 8 seven-segment drives and decimal point drive that source current to the display. Positive Supply Voltage. Connect to +2.7 to +5.5V supply. Serial-Data Output. The data into pin SDI is valid at pin SDO 16 clock cycles later. This pin is used to daisy-chain several devices and is never high-impedance.
SCL SEGA:SEG G, SEGDP VDD SDO
14 15-18, 20-23 19 24
11 12-15, 17-20 16 21
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DIG6
DIG7
LD
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AS1116
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter VDD to GND Input Voltage Range All other pins to GND DIG0:DIG7 Sink Current SEGA:SEGG, SEGDP Humidity Electrostatic Discharge Digital outputs All other pins 100 88 30.5 -40 -55 +85 150 5 Min -0.3 -0.3 Max 7 7 or VDD + 0.3 500 100 85 1000 1000 Units V V mA mA % V V mA C/W C/W C C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020D "Moisture/ Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). Non-condensing Norm: MIL 833 E method 3015 EIA/JESD78 on PCB, QSOP-24 package on PCB, TQFN(4x4)-24 package Notes
Current
Latch-Up Immunity Thermal Resistance JA Ambient Temperature Storage Temperature
Package Body Temperature
+260
C
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AS1116
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = 2.7 to 5.5V, RSET = 9.53k, TAMB = -40 to +85C, typ. values @ TAMB = +25C, VDD = 5.0V (unless otherwise specified). Table 3. Electrical Characteristics Symbol VDD IDDSD Parameter Operating Supply Voltage Shutdown Supply Current All digital inputs at VDD or GND, TAMB = +25C RSET = open circuit. IDD fOSC IDIGIT ISEG ISEG ISEG Operating Supply Current Display Scan Rate Digit Drive Sink Current Segment Drive Source Current Segment Drive Current Matching Segment Drive Source Current All segments and decimal point on; ISEG = -40mA. 8 digits scanned VOUT = 0.65V VDD = 5.0V, VOUT = (VDD -1V) Average Current 0.6 320 -37 -42 3 47 -47 Conditions Min 2.7 0.2 0.35 335 0.8 1.2 Typ Max 5.5 2 0.6 mA kHz mA mA % mA Unit V A
Table 4. Logic Inputs/Outputs Characteristics Symbol IIH, IIL VIH VIL Parameter Input Current SDI, SCL, LD Logic High Input Voltage Logic Low Input Voltage Conditions VIN = 0V or VDD 4.5V < VDD < 5.5V 2.7V < VDD < 4.5V VDD = 5.0V VDD = 3.0V SDO, ISOURCE = -1mA, VDD = 5.0V SDO, ISOURCE = -1mA, VDD = 3.0V SDO, ISINK = 1mA SDI, SCL, LD VDD - 1 V VDD - 0.5 0.4 1 0.7x 0.75x 0.8x VDD VDD VDD 0.1x 0.15x 0.05x VDD VDD VDD V V V V Min -1 0.6 x VDD 0.7 x VDD 0.8 0.6 Typ Max 1 Unit A V V V
VOH VOL VI
Output High Voltage Output Low Voltage Hysteresis Voltage Open Detection Level Threshold Short Detection Level Threshold
Table 5. SPI Timing Characteristics Symbol tCP tCH tCL tCSS tCSH tDS tDH tDO tLDCK tCSW tDSPD Parameter SCL Clock Period SCL Pulse Width High SCL Pulse Width Low LD to SCL Rise Setup Time SCL Rise to LD Rise Hold Time SDI Setup Time SDI Hold Time Output Data Propagation Delay LD Rising Edge to SCL Rising Edge Minimum LD Pulse High Data-to-Segment Delay Conditions Min 100 20 20 25 10 0 5 20 20 2.25 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ms
CLOAD = 50pF
25
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AS1116
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
7 Typical Operating Characteristics
RSET = 9.53k, VRset = VDD; Figure 3. Display Scan Rate vs. Supply Voltage;
980 960 940
Figure 4. Display Scan Rate vs. Temperature;
980 960 940
fosc (Hz) .
920 900 880
Tamb = - 40C
fosc (Hz) .
920 900 880
Vdd = 2.7V Vdd = 4V Vdd = 5V Vdd = 5.5V
860 840 2.7 3.1 3.5 3.9 4.3
Tamb = + 25C Tamb = + 85C
860 840 -40
4.7
5.1
5.5
-15
10
35
60
85
Vdd (V) Figure 5. Segment Current vs. Temperature;
60 50
Tamb (C) Figure 6. Segment Current vs. RSET;
50
Vseg Vseg Vseg Vseg = 4V; Vdd = 5V = 3V; Vdd = 5V = 2V; Vdd = 5V = 1.7V; Vdd = 2.7V
40
Iseg (mA) .
Iseg (mA) .
Vseg Vseg Vseg Vseg = 1.7V; Vdd = 2.7V = 1.7V; Vdd = 5V = 3V; Vdd = 5V = 4V; Vdd = 5V
40 30 20 10 0 -40
30
20
10
0 -15 10 35 60 85 0 10 20 30 40 50 60 70 80 90
Tamb (C) Figure 7. Segment Current vs. Supply Voltage;
60 50
Rset (kOhm) Figure 8. Segment Current vs. VDD; VRset = 2.8V
50 45 40 35
Vseg Vseg Vseg Vseg = 1.7V = 2V = 2.3V = 3.1V
Iseg (mA) .
Iseg (mA) .
Vseg = 1.7V Vseg = 3V Vseg = 4V
40 30 20 10 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
30 25 20 15 10 5 0 2.7 3 3.3 3.6 3.9 4.2
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AS1116
Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s
Figure 9. VDIGIT vs. IDIGIT
0.4
Figure 10. Input High Level vs. Supply Voltage
3.5 3
0.3
2.5
Vdig (V) .
Vih (V) .
Vdd Vdd Vdd Vdd Vdd = 2.7V = 3.3V = 4V = 5V = 5.5V
2 1.5 1 0.5 0
0.2
0.1
0 0 0.05 0.1 0.15
Idig (A)
0.2
0.25
0.3
0.35
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Vdd (V)
Figure 11. ISEG vs. VSEG; VDD = 5V
50 45 40 35
Rext Rext Rext Rext Rext = 10k = 13k = 18k = 30k = 56k
Figure 12. ISEG vs. VSEG; VDD = 4V
50 45 40 35
Rext Rext Rext Rext Rext = 8k2 = 10k = 13k = 18k = 30k
Iseg (mA) .
30 25 20 15 10 5 0 2 2.5 3 3.5 4 4.5 5
Iseg (mA) .
30 25 20 15 10 5 0 1 1.5 2 2.5 3 3.5 4
Vseg (V)
Vseg (V)
Figure 13. ISEG vs. VSEG; VDD = 3.3V
50 45 40 35
Rext Rext Rext Rext Rext = 6k8 = 8k2 = 10k = 13k = 18k
Figure 14. ISEG vs. VSEG; VDD = 2.7V
50 45 40 35
Rext Rext Rext Rext Rext = 4k7 = 5k6 = 6k8 = 10k = 13k
Iseg (mA) .
30 25 20 15 10 5 0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2
Iseg (mA) .
30 25 20 15 10 5 0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6
Vseg (V)
Vseg (V)
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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
Block Diagram
Figure 15. Block Diagram (QSOP-24 Package)
Open/Short Detection + - 19 + VDD 13 ISET -
VDD
RSET
Oszillator
8
15-18, 20-23 SEGA-G, SEGDP
Digital Control Logic
11 LD 1 SDI 14 SCL 24 SDO
8
2-5, 7-10 DIG0 to DIG7
(PWM, Debounce,....)
Registers
SPI Interface Data - Registers Control - Registers Scan - Registers
6 GND
AS1116
Figure 16. ESD Structure
valid for the pins: - SDI - SCL - SDO - LD - ISET - SEGA-G, SEGDP
VDD
VDD valid for the pins: - DIG0 to DIG7
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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Serial-Addressing Format
The AS1116 contains a 16bit SPI interface to access the internal data and control registers of the device (see Digitand Control-Registers on page 9). The SPI interface is driven with the rising edge of SCL. A falling edge on LD signal indicates the beginning of an access on the SPI interface, the rising edge on LD determines an access on SPI. An access must consist of exactly 16bits for write operation and 8bits for read operation. Timing restrictions on the SPI interface pins are defined in Figure 18. Table 6 shows the structure of the 16bit command word for writing data, Table 7 the 8bit command word for read operation. D0 (write operation) / D8 (read operation) is the first bit to shift into the SPI interface after the falling edge of LD, is the last bit to write to SPI before rising edge of LD. At a read operation an 8bit operation is executed. At the first rising edge of SCL after the rising edge of LD D7 of addressed register is written to SDO pin. At the next rising edge of SCL D6 is written to SDO pin. LD must be kept high during reading data from a internal data or control register of AS1116.
Table 6. 16-Bit Serial Data Format D0 LSB D1 D2 D3 D4 Data D5 D6 D7 MSB D8 D9 D10 D11 D12 Register Address (see Table 7) D13 0 D14 R/W D15 X
Figure 17. Read operation
1 8 9 10 16
SCL LD SDO
D7 D4 D3 D2 D1 D0
D6
D5
Figure 18. Interface Timing
LD
tCSW tCSS tCP tCL tCH tCSH tLDCK
SCL
tDS
tDH
SDI
D0
D1
D14
D15
tDO
SDO
Initial Power-Up
On initial power-up, the AS1116 registers are reset to their default values, the display is blanked, and the device goes into shutdown mode. At this time, all registers should be programmed for normal operation.
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control Register (see page 13) is set to the minimum values.
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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Shutdown Mode
The AS1116 devices feature a shutdown mode, where they consume only 200nA (typ) current. Shutdown mode is entered via a write to the Shutdown Register (see Table 8). For the AS1116, at that point, all segment current sources and digital drivers are switched off, so that all segments are blanked.
Note: During shutdown mode the Digit-Registers maintain their data.
Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display (repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic input should be at GND or VDD (CMOS logic level). When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdown Register bit D7 (page 10) = 0.
Note: When Shutdown Register bit D7 = 1, the Feature Register is left unchanged when entering or leaving shutdown mode. If the AS1116 is used with an external clock, Shutdown Register bit D7 should be set to 1 when writing to the Shutdown Register.
Digit- and Control-Registers
The AS1116 devices contain 8 Digit-Registers,11 control-registers and 8 diagnostic-registers, which are listed in Table 7. All registers are selected using a 8-bit address word, and communication is done via the serial interface.
!
Digit Registers - These registers are realized with an on-chip 64-bit memory. Each digit can be controlled directly without rewriting the whole register contents. Control Registers - These registers consist of decode mode, display intensity, number of scanned digits, shutdown, display test and features selection registers.
!
Table 7. Register Address Map Type Register Address D15 D14 D13 D12 D11 D10 D9 D8 D7:D0 Page
No-Op Digit 0 Digit 1
Digit Register
X X X X X X X X X X X X X X X X X X X X
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 (see Table 19 on page 14) (see Table 13 on page 12) (see Table 17 on page 13) (see Table 17 on page 13) (see Table 17 on page 13) (see Table 17 on page 13) (see Table 9 on page 10) (see Table 16 on page 13) (see Table 18 on page 13) (see Table 8 on page 10) (see Table 10 on page 11, Table 11 on page 11 and Table 12 on page 11)
14 N/A N/A N/A N/A N/A N/A N/A N/A 10 13 13 9 N/A 14 10
Digit 2 Digit 3 Digit 4 Digit 5 Digit 6 Digit 7 Decode-Mode Global Intensity Scan Limit
Control Register
Shutdown Not Used Feature Display Test Mode DIG0:DIG1 Intensity DIG2:DIG3 Intensity DIG4:DIG5 Intensity DIG6:DIG7 Intensity
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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 7. Register Address Map Type Register Address D15 D14 D13 D12 D11 D10 D9 D8 D7:D0 Page
Diagnostic Digit 0
Diagnostic Register
X X X X X X X X
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1
1 1 1 0 0 0 0 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
N/A N/A N/A N/A N/A N/A N/A N/A
Diagnostic Digit 1 Diagnostic Digit 2 Diagnostic Digit 3 Diagnostic Digit 4 Diagnostic Digit 5 Diagnostic Digit 6 Diagnostic Digit 7
Note: Write operation: D14=0; Read operation: D14=1.
The Shutdown Register controls AS1116 shutdown mode.
Table 8. Shutdown Register Format (Address (HEX) = 0x0C)) Mode Register Data HEX Code D7 D6 D5 D4 D3 D2 D1 D0 0x00 0 X X X X X X 0 0x80 1 X X X X X X 0 0x01 0 X X X X X X 1 0x81 1 X X X X X X 1
Shutdown Mode, Reset Feature Register to Default Settings Shutdown Mode, Feature Register Unchanged Normal Operation, Reset Feature Register to Default Settings Normal Operation, Feature Register Unchanged
Decode Enable Register (0x09)
The Decode Enable Register sets the decode mode. BCD/HEX decoding (either BCD code - characters 0:9, E, H, L, P, and -, or HEX code - characters 0:9 and A:F) is selected by bit D2 (page 14) of the Feature Register. The Decode Enable Register is used to select the decode mode or no-decode for each digit. Each bit in the Decode Enable Register corresponds to its respective display digit (i.e., bit D0 corresponds to digit 0, bit D1 corresponds to digit 1 and so on). Table 10 lists some examples of the possible settings for the Decode Enable Register bits.
Note: A logic high enables decoding and a logic low bypasses the decoder altogether.
When decode mode is used, the decoder looks only at the lower-nibble (bits D3:D0) of the data in the Digit-Registers, disregarding bits D6:D4. Bit D7 sets the decimal point (SEG DP) independent of the decoder and is positive logic (bit D7 = 1 turns the decimal point on). Table 10 lists the code-B font; Table 11 lists the HEX font. When no-decode mode is selected, data bits D7:D0 of the Digit-Registers correspond to the segment lines of the AS1116. Table 12 shows the 1:1 pairing of each data bit to the appropriate segment line.
Table 9. Decode Enable Register Format Examples Decode Mode Register Data HEX Code D7 D6 D5 D4 D3 D2 D1 D0 0x00 0 0 0 0 0 0 0 0 0x01 0 0 0 0 0 0 0 1 0x07 0 0 0 0 0 1 1 1 0x3F 0 0 1 1 1 1 1 1 0x25 0 0 1 0 0 1 0 1
No decode for digits 7:0 Code-B/HEX decode for digit 0. No decode for digits 7:1 Code-B/HEX decode for digit 0:2. No decode for digits 7:3 Code-B/HEX decode for digits 0:5. No decode for digits 7:6 Code-B/HEX decode for digits 0,2,5. No decode for digits 1, 3, 4, 6, 7
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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 10. Code-B Font Register Data Register Data Register Data CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acter D7 D6:D4 D3 D2 D1 D0
X
0
0
0
0
X
0
1
1
0
X
1
1
0
0
X
0
0
0
1
X
0
1
1
1
X
1
1
0
1
X
0
0
1
0
X
1
0
0
0
X
1
1
1
0
X
0
0
1
1
X
1
0
0
1
*
X
1
1
1
1
X
0
1
0
0
X
1
0
1
0
1
X
X
X
X
X
X
*
0
1
0
1
X
1
0
1
1
The decimal point can be enabled with every character by setting bit D7 = 1. Table 11. HEX Font
Register Data Register Data Register Data CharCharCharacter D7 D6:D4 D3 D2 D1 D0 acter D7 D6: D4 D3 D2 D1 D0 acter D7 D6:D4 D3 D2 D1 D0
X
0
0
0
0
X
0
1
1
0
X
1
1
0
0
X
0
0
0
1
X
0
1
1
1
X
1
1
0
1
X
0
0
1
0
X
1
0
0
0
X
1
1
1
0
X
0
0
1
1
X
1
0
0
1
*
X
1
1
1
1
X
0
1
0
0
X
1
0
1
0
1
X
X
X
X
X
X
*
0
1
0
1
X
1
0
1
1
The decimal point can be enabled with every character by setting bit D7 = 1.
Table 12. No-Decode Mode Data Bits and Corresponding Segment Lines
Corresponding Segment Line
Figure 19. Standard 7-Segment LED
D7 DP
D6 A
D5 B
D4 C
D3 D
D2 E
D1 F
D0 G
F
A G D
B
E
C DP
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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Display-Test Mode
The AS1116 can detect open or shorted LEDs. Readout of either open LEDs (D2=1) or short LEDs (D1=1) is possible, as well as a OR relation of open and short (D1=D2=1). After a dignostic run bit D4 can be read to clearify if an error occurred before reading out detailed diagnostic data.
Note: All settings of the digit- and control-registers are maintained. Table 13. Testmode Register Summary D7 X D6 REXT_short D5 REXT_open D4 LED_global D3 LED_test D2 LED_open D1 LED_short D0 DISP_test
Table 14. Testmode Register Bit Description (Address (HEX) = 0x0F)) Addr: 0x0F Bit Bit Name Default Access Address D7:D0
D0
DISP_test
0
W
Optical display test. (Testmode for external visual test.) 0: Normal operation; 1: Run display test (All digits are tested independently from scan limit & shutdown register.) Starts a test for shorted LEDs. (Can be set together with D2) 0: Normal operation; 1: Activate testmode Starts a test for open LEDs. (Can be set together with D1) 0: Normal operation; 1: Activate testmode Indicates an ongoing open/short LED test 0: No ongoing LED test; 1: LED test in progress Indicates that the last open/short LED test has detected an error 0: No error detected; 1: Error detected Checks if external resistor REXT is open 0: REXT correct; 1: REXT is open Checks if external resistor REXT is shorted 0: REXT correct; 1: REXT is shorted Not used
D1 D2 D3 D4 D5 D6 D7
LED_short LED_open LED_test LED_global REXT_open REXT_short
0 0 0 0 0 0 0
W W R R R R -
LED Diagnostic Registers
These eight registers contain the result of the LED open/short test for the individual LED of each digit.
Table 15. LED Diagnostic Register Address Register HEX Address 0x14 0x15 0x16 0x17 Segment Digit D7 D6 D5 D4 D3 D2 D1 D0 Register HEX Address 0x18 0x19 0x1A 0x1B Segment Digit D7 D6 D5 D4 D3 D2 D1 D0
DIG0 DIG1 DP DIG2 DIG3
A
B
C
D
E
F
G
DIG4 DIG5 DP DIG6 DIG7
A
B
C
D
E
F
G
Note: If more than 2 shorts occure in the LED array, detection of individual LED fault could become limited to blocs.
Intensity Control Register (0x0A)
The brightness of the display can be controlled by digital means using the Intensity Control Registers and by analog means using RSET (see Selecting RSET Resistor Value and Using External Drivers on page 15). The intensity can be controlled globally for all digits, or for each digit individually. The global intensity command will write intensity data to all four individual brightness registers, while the individual intesity command will only write to the associated individual intensity register.
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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the Intensity Control Register. The modulator scales the average segment-current in 16 steps from a maximum of 15/16 down to 1/16 of the peak current set by RSET.
Table 16. Intensity Register Format Duty Cycle HEX Code MSB 0 0 0 0 0 0 0 0 Register Data D2 D1 LSB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Duty Cycle HEX Code MSB 1 1 1 1 1 1 1 1 Register Data D2 D1 LSB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
1/16 (min on) 2/16 3/16 4/16 5/16 6/16 7/16 8/16
0xX0 0xX1 0xX2 0xX3 0xX4 0xX5 0xX6 0xX7
9/16 10/16 11/16 12/16 13/16 14/16 15/16 15/16 (max on)
0xX8 0xX9 0xXA 0xXB 0xXC 0xXD 0xXE 0xXF
Table 17. Intensity Register Address Register HEX Address 0x0A 0x10 0x11 0x12 0x13 Register Data Type Global Digit Digit Digit Digit D7:D4 X Digit 1 Intensity Digit 3 Intensity Digit 5 Intensity Digit 7 Intensity D3:D0 Global Intensity Digit 0 Intensity Digit 2 Intensity Digit 4 Intensity Digit 6 Intensity
Scan-Limit Register (0x0B)
The Scan-Limit Register controls which of the digits are to be displayed. When all 8 digits are to be displayed, the update frequency is typically 0.8kHz. If the number of digits displayed is reduced, the update frequency is increased. The frequency can be calculated using 8fOSC/N, where N is the number of digits. Since the number of displayed digits influences the brightness, RSET should be adjusted accordingly.
Note: To avoid differences in brightness this register should not be used to blank parts of the display (leading zeros). Table 18. Scan-Limit Register Format (Address (HEX) = 0x0B)) Scan Limit Register Data HEX Code D7:D3 D2 D1 D0 0xX0 X 0 0 0 0xX1 X 0 0 1 0xX2 X 0 1 0 0xX3 X 0 1 1 Scan Limit Register Data HEX Code D7:D3 D2 D1 D0 0xX4 X 1 0 0 0xX5 X 1 0 1 0xX6 X 1 1 0 0xX7 X 1 1 1
Display digit 0 only Display digits 0:1 Display digits 0:2 Display digits 0:3
Display digits 0:4 Display digits 0:5 Display digits 0:6 Display digits 0:7
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AS1116
Datasheet - D e t a i l e d D e s c r i p t i o n
Feature Register (0x0E)
The Feature Register is used for enabling various features including switching the device into external clock mode, applying an external reset, selecting code-B or HEX decoding, enabling or disabling blinking, enabling or disabling the SPI-compatible interface, setting the blinking rate, and resetting the blink timing.
Note: At power-up the Feature Register is initialized to 0. Table 19. Feature Register Summary D7 D6 D5 D4 D3 D2 D1 D0
blink_ start
sync
blink_ freq_sel
blink_en
NU
decode_sel
reg_res
clk_en
Table 20. Feature Register Bit Descriptions (Address (HEX) = 0xXE) Addr: 0xXE Bit Feature Register Enables and disables various device features. Bit Name Default Access Bit Description External clock active. clk_en 0 R/W 0 = Internal oscillator is used for system clock. 1 = Pin CLK of the serial interface operates as system clock input. Resets all control registers except the Feature Register. 0 = Reset Disabled. Normal operation. reg_res 0 R/W 1 = All control registers are reset to default state (except the Feature Register) identically after power-up. Note: The Digit Registers maintain their data. Selects display decoding for the selected digits (Table 9 on page 10). decode_sel 0 = Enable Code-B decoding (see Table 10 on page 11). 0 R/W 1 = Enable HEX decoding (see Table 11 on page 11). NU Not used Enables blinking. blink_en 0 R/W 0 = Disable blinking. 1 = Enable blinking. Sets blink with low frequency (with the internal oscillator enabled): blink_freq_sel 0 = Blink period typically is 1 second (0.5s on, 0.5s off). 0 R/W 1 = Blink period is 2 seconds (1s on, 1s off). Synchronizes blinking on the rising edge of pin LD. The multiplex and blink timing counter is cleared on the rising edge of pin LD. By setting sync 0 R/W this bit in multiple devices, the blink timing can be synchronized across all the devices. Start Blinking with display enabled phase. When bit D4 (blink_en) is set, bit D7 determines how blinking starts. blink_start 0 R/W 0 = Blinking starts with the display turned off. 1 = Blinking starts with the display turned on.
D0
D1
D2 D3 D4 D5
D6
D7
No-Op Register (0xX0)
The No-Op Register is used when multiple AS1116 devices are cascaded in order to support displays with more than 8 digits. The cascading must be done in such a way that all SDO pins are connected to SDI of the next AS1116 (see Figure 20 on page 16). The LD and SCL signals are connected to all devices. For example, if five devices are cascaded, in order to perform a write operation to the fifth device, the write-command must be followed by four no-operation commands. When the LD signal goes high, all shift registers are latched. The first four devices will receive no-operation commands and only the fifth device will receive the intended operation command, and subsequently update its register.
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AS1116
Datasheet - Ty p i c a l A p p l i c a t i o n
9 Typical Application
Selecting RSET Resistor Value and Using External Drivers
Brightness of the display segments is controlled via RSET. The current that flows between VDD and ISET defines the current that flows through the LEDs. Segment current is about 200 times the current in ISET. Typical values for RSET for different segment currents, operating voltages, and LED voltage drop (VLED) are given in Table 21 & Table 22. The maximum current the AS1116 can drive is 47mA. If higher currents are needed, external drivers must be used, in which case it is no longer necessary that the devices drive high currents.
Note: The display brightness can also be logically controlled (see Intensity Control Register (0x0A) on page 12). Table 21. RSET vs. Segment Current and LED Forward Voltage, VDD = 2.7V & 3.3V & 3.6V ISEG (mA) VLED
1.5V 2.0V 1.5V
VLED
2.0V 2.5V 1.5V
VLED
2.0V 2.5V 3.0V
40 30 20 10
5k 6.9k 10.7k 22.2k
4.4k 5.9k 9.6k 20.7k
6.7k 9.1k 13.9k 28.8k
6.4k 8.8k 13.3k 27.7k
5.7k 8.1k 12.6k 26k
7.5k 10.18k 15.6k 31.9k
7.2k 9.8k 15k 31k
6.6k 9.2k 14.3k 29.5k
5.5k 7.5k 13k 27.3k
VDD = 2.7V
VDD = 3.3V
Table 22. RSET vs. Segment Current and LED Forward Voltage, VDD = 4.0V & 5.0V ISEG (mA) VLED
1.5V 2.0V 2.5V 3.0V 3.5V 1.5V 2.0V
VDD = 3.6V
VLED
2.5V 3.0V 3.5V 4.0V
40 30 20 10
8.6k 8.3k 11.6k 11.2k 17.7k 17.3k 36.89k 35.7k
7.9k 7.6k 5.2k 10.8k 9.9k 7.8k 16.6k 15.6k 13.6k 34.5k 32.5k 29.1k
11.35k 15.4k 23.6k 48.9k
11.12k 15.1k 23.1k 47.8k
10.84k 10.49k 10.2k 9.9k 14.7k 14.4k 13.6k 13.1k 22.6k 22k 21.1k 20.2k 46.9k 45.4k 43.8k 42k
VDD = 4.0V
Calculating Power Dissipation
The upper limit for power dissipation (PD) for the AS1116 is determined from the following equation:
PD = (VDD x 5mA) + (VDD - VLED)(DUTY x ISEG x N) Where: VDD is the supply voltage. DUTY is the duty cycle set by intensity register (page 13). N is the number of segments driven (worst case is 8) VLED is the LED forward voltage ISEG = segment current set by RSET Dissipation Example: ISEG = 40mA, N = 8, DUTY = 15/16, VLED = 2.2V at 40mA, VDD = 5V PD = 5V(5mA) + (5V - 2.2V)(15/16 x 40mA x 8) = 0.865W (EQ 2) (EQ 3) (EQ 1)
Thus, for a QSOP-24 package JA = +88C/W, the maximum allowed TAMB is given by:
TJ,MAX = TAMB + PD x JA = 150C = TAMB + 0.865W x 88C/W (EQ 4)
In this example the maximum ambient temperature must stay below 73.88C.
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VDD = 5.0V
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AS1116
Datasheet - Ty p i c a l A p p l i c a t i o n
8x8 Dot Matrix Mode
The application example in Figure 20 shows the AS1116 in the 8x8 LED dot matrix mode. The LED columns have common cathodes and are connected to the DIG0:7 outputs. The rows are connected to the segment drivers. Each of the 64 LEDs can be addressed separately. The columns are selected via the digits as listed in Table 7 on page 9. The Decode Enable Register (see page 10) must be set to `00000000' as described in Table 9 on page 10. Single LEDs in a column can be addressed as described in Table 12 on page 11, where bit D0 corresponds to segment G and bit D7 corresponds to segment DP.
Note: For a multiple-digit dot matrix, multiple AS1116 devices can be cascaded easily. Figure 20. Application Example as LED Dot Matrix Driver
VDD 2.7 to 5V 9.53k ISET I/O I/O P I/O I/O SDI SCL LD SDO Diagnostic readback: open & shorted LEDs
DIG0 to DIG7 SEG A to G SEP DP
AS1116
Diode Arrangement
GND
Supply Bypassing and Wiring
In order to achieve optimal performance the AS1116 should be placed very close to the LED display to minimize effects of electromagnetic interference and wiring inductance. Furthermore, it is recommended to connect a 10F electrolytic and a 0.1F ceramic capacitor between pins VDD and GND to avoid power supply ripple (see Figure 20 on page 16).
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AS1116
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
The AS1116 is available in the QSOP-24 package.
Figure 21. QSOP-24 Package
Symbol A A1 A2 b C D E E1 e h L
Min Max 1.35 1.75 0.10 0.25 1.37 1.57 0.20 0.30 0.19 0.25 8.55 8.74 5.79 6.20 3.81 3.99 0.635 BSC 0.22 0.49 0.40 1.27 0 8
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AS1116
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Figure 22. TQFN(4x4)-24 Package
19
20
21
22
23
24
18 17 16 15 14 13
1 2 3 4 5 6
12
11
10
9
8
7
m m
Symbol A A1 A3 b D E D2 E2
Min 0.50 0.00
Typ 0.55
Max 0.60 0.05
0.18
2.70 2.70
0.152REF 0.23 4.00BSC 4.00BSC 2.80 2.80
0.28
2.90 2.90
Symbol e L L1 aaa bbb ccc ddd eee
Min
0.30 0.00
Typ 0.50BSC 0.35
Max
0.40 0.10
0.10 0.10 0.10 0.05 0.08
Notes:Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals.
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters; angles in degrees. 3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional.
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AS1116
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as the standard products shown in Table 23.
Table 23. Ordering Information Ordering Code Marking Desciption 64 LED Driver with Detailed Error Detection 64 LED Driver with Detailed Error Detection Delivery Form Package
AS1116-BSST AS1116-BQFT
AS1116 ASR9
Tape and Reel Tape and Reel
QSOP-24 TQFN(4x4)-24
All devices are RoHS compliant and free of halogene substances.
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AS1116
Datasheet
Copyrights
Copyright (c) 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
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For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact-us
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